VP, IntelDr. Jun He is Intel VP @ Technology and Manufacturing Group, including both fab and packaging at Intel Corporation. Dr. He is responsible for all aspects of quality & reliability across all Intel's process technologies. His global engineering organization owns design rule definition & implementation, reliability of Si/assembly/test technology development and all Intel manufacturing quality serving various end markets.
Dr. He has over 20 years industry experience directly engaged in technology development on Si fab, assembly and test process. He spent his earlier Intel career in Logic Technology Development division at Oregon from 130nm to 22nm nodes. Particularly he oversaw the entire technology qualification and production ramp of Intel's 32nm logic technology.
He has 40 technical publications and holds more than 30 U.S. /Foreign patents. His key contribution to the semiconductor industry includes laser assisted die singulation enabling low-k dielectric; die edge damage monitor; ultra-high density metal fuse technology; innovative passivation process for Redistribution Interconnects and tamper resistant fuse design/architecture for secure content markets. He was honored with 3 Intel Achievement Awards, in 2003, 2007 and 2009, respectively.
Dr. He received his B. S. degree in Physics and Ph.D. in Material Science from the University of California, Santa Barbara.